1. Field of the Invention
The present invention relates to a method and apparatus for reducing the number of power supply ports of an integrated circuit (IC) apparatus. More particularly, the present invention relates to a method and apparatus for reducing the number of power supply ports of an IC apparatus by reducing the number of bus outputs that are simultaneously switched, with the use of a master clock signal and a slave clock signal, which is a variation of the master clock signal.
2. Description of the Related Art
Recently, as an increasing number of integrated circuits (ICs) are designed in a system-on-chip (SOC) manner, the size of ICs increases. In addition, an increase in the size of ICs results in an increase in the number of power supply ports for such ICs because as the number of buses that switch their respective states at a predetermined moment of time increases, the amount of current increases.
FIG. 1 is a block diagram of a conventional IC apparatus 180 with simultaneously switching output. Referring to FIG. 1, the conventional IC apparatus 180 includes first, second, third, through n-th external device controllers 100, 110, 120, and 130, a multiplexer 140, and a plurality of output buffers 150, 160, and 170.
The first, second, third, and n-th external device controllers 100, 110, 120, and 130 control external devices, such as external memories and analog-to-digital converters, by using control signals, data signals, and address signal lines.
The multiplexer 140 allows the first, second, third, and n-th external device controllers 100, 110, 120, and 130 to share buses in the conventional IC apparatus 180.
The output buffers 150, 160, and 170, which are bi-directional buffers, insulate the conventional IC apparatus 180 from the external devices and compensates for lack of current.
In FIG. 1, the first, second, third, and n-th external device controllers 100, 110, 120, and 130 may simultaneously operate in a given clock cycle because they may share buses together or exist on different levels of bus hierarchy using different buses. An address signal bus port, a control signal bus port, and a data signal bus output port for each of the buses that can operate simultaneously operate in synchronization of an inner bus reference clock frequency.
For example, in a case where in a 32-bit system, a ROM controller and an input/output (I/O) controller share buses, and first and second SDRAM controllers have their own buses, a total of 96 data signals can be simultaneously switched, and thus a total of 96 data ports are necessary. Taking address and control signal ports as well as the data signals into consideration, a total number of output ports that are simultaneously switched increases considerably.
In the prior art, even a 32-bit system with only three independent buses may have a considerable number of output ports that are simultaneously switched. In some cases, all of the output ports of the 32-bit system can be switched at the same time, in which case, the number of power supply ports exponentially increases. In addition, in the case of using a 64-bit system, instead of the 32-bit system, or using a multi-level internal bus structure, the number of output ports that are simultaneously switched can increase more considerably, a package for an IC apparatus can be more difficult to choose, and the price of the IC apparatus can become higher.